REJ09B0177-0300
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
32
SH-2E SH7059 F-ZTAT , SH7058S F-ZTAT
TM
TM
Hardware Manual
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7000 Series
Rev.3.00 Revision date: Mar. 12, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
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General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.
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Preface
The SH7059/SH7058S is a single-chip RISC (reduced instruction set computer) microcomputer that has the 32-bit internal architecture CPU, SH-2E, as its core, and also includes peripheral functions necessary for system configuration. This LSI is equipped with on-chip peripheral functions necessary for system configuration, including a floating-point unit (FPU), large-capacity ROM and RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), controller area network (HCAN), A/D converter, and I/O ports, therefore, it can be used as a microprocessor built in a high-level control system. This LSI is an F-ZTAT* (Flexible Zero Turn-Around Time) version with flash memory as its on-chip ROM, and it can rapidly and flexibly deal with each situation on an application system with fluid specifications from an early stage of mass production to full-scale production. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Target users: This manual was written for users who will be using the SH7059 F-ZTAT and SH7058S F-ZTAT in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical curcuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7059 F-ZTAT and SH7058S F-ZTAT to the above users. Refer to the SH-2E Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-2E Software Manual. Rule: Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right.
Releated Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7059 F-ZTAT and SH7058S F-ZTAT manuals:
Document Title SH-2E SH7059 F-ZTAT , SH7058S F-ZTAT SH-2E Software Manual
TM TM
Document No. Hardware Manual This manual REJ09B0316-0200
Rev.3.00 Mar. 12, 2008 Page v of xc REJ09B0177-0300
User's manuals for development tools:
Document Title SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SuperH RISC engine Simulator/Debugger User's Manual SuperH RISC engine Simulator/Debugger (for SPARC solaris, HP9000 Series 700) User's Manual High-performance Embedded Workshop V.4.03 User's Manual High-performance Embedded Workshop V.4.04 User's Manual
TM TM TM
Document No. REJ10B0047-0100H REJ10B0210-0400 ADE-702-203 REJ10J1586-0100 REJ10J1737-0100
Application note:
Document Title C/C++ Compiler Document No. REJ05B0463-0300
All trademarks and registered trademarks are the property of their respective owners.
Rev.3.00 Mar. 12, 2008 Page vi of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H) All 1.1 Features Table 1.1 SH7058 Features 3,4 Clock pulse generator (CPG/PLL) * On-chip clock-multiplication PLL circuit (x 4, x 8) Interrupt controller (INTC) * 117 internal interrupt sources (ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC x 1, CMT x 2, HCAN-II x 8, H-UDI x 1) Direct memory access controller (DMAC) (4 channels) * DMA transfer requests by on-chip modules SCI, A/D converter, ATU-II, HCAN-II All Synchronous serial communication unit (SSU) added 1.1 Features Table 1.1 SH7059 Features CPG/PLL, INTC, DMAC, and AUD amended Clock pulse generator (CPG/PLL) * On-chip clock-multiplication PLL circuit ( x 8) Interrupt controller (INTC) * 123 internal interrupt sources (ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC x 1, CMT x 2, HCAN-II x 8, H-UDI x 1, SSU x 6) Direct memory access controller (DMAC) (4 channels) * DMA transfer requests by on-chip modules SCI, A/D converter, ATU-II, HCAN-II, SSU SH7058S/SH7059
Synchronous serial communication unit (SSU) (2 channels) * * * * * * * * Advanced user debugger (AUD) * RAM monitor mode Data input/output frequency: 10 MHz or less Support for master mode Synchronous serial communications with devices having a different clock phase or polarity Choice of 8/16/32-bit width of transmit/receive data Full-duplex communication capability Continuous serial communications Choice of LSB-first or MSB-first transfer Choice of clock source from among seven internal clocks Five interrupt sources
Advanced user debugger (AUD) * RAM monitor mode Data input/output frequency: 1/8 or less of the internal operating frequency ()
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 1.1 Features Table 1.1 SH7058 Features 6,7 ROM * * 1-MB flash memory 1-MB divided into 16 blocks Small blocks: 4 kB x 8 Medium block: 96 kB x 1 Large blocks: 128 kB x 7 1.1 Features Table 1.1 SH7059 Features ROM, and RAM amended ROM * 1MB Flash memory (SH7058S), 1.5MB Flash memory (SH7059) * Flash memory: Divided into 16 blocks SH7058S 4KB x 8 blocks 96KB x 1 block 128KB x 7 blocks SH7059 * 4KB x 8 blocks 96KB x 1 block 128KBx3 blocks 256KBx4 blocks block) SH7058S/SH7059
* 1-MB flash memory 1-MB divided into 16 blocks 1-MB divided into 16 blocks Small blocks: 4 kB x 8 Medium block: 96 kB x 1 Large blocks: 128 kB x 7 * RAM emulation function (using 4 kB small block)
RAM emulation function (using 4 KB
RAM * 48 kB SRAM
RAM * 48KB (SH7058S), 80KB (SH7059) SRAM 1.2 Block Diagram Figure 1.1 Block Diagram Figure amended Port/control signals PF15/BREQ/SCS0 PF14/BACK/SCS1 ROM (Flash) 1.5MB (SH7059) 1.0MB (SH7058S)
1.2 Block Diagram Figure 1.1 Block Diagram 7 Port/control signals PF15/BREQ PF14/BACK ROM (Flash) 1MB
RAM 48 kB
RAM 80KB (SH7059) 48KB (SH7058S)
SCI (5 channels) HCAN-II (2 channels)
SCI (5 channels) SSU (2 channels) HCAN-II (2 channels)
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 1.2 Block Diagram Figure 1.1 Block Diagram 7 Port PL7/SCK2 PL12/IRQ4 PL13/IRQOUT PA14/TxD0 PA15/RxD0 PB13/SCK0 PB15/PULS5/SCK2 PC2/TxD2 PC3/RxD2 XTAL Clock pulse generator Peripheral address bus (9 bits) 1.3.1 Pin Arrangement Figure 1.2 Pin Arrangement (FP-256H) 8 45 PF14/BACK 46 PF15/BREQ 143 PA14/TxD0 144 PA15/RxD0 160 PB13/SCK0 164 PB15/PULS5/SCK2 167 PC2/TxD2 168 PC3/RxD2 223 PL7/SCK2 230 PL12/IRQ4 231 PL13/IRQOUT Figure 1.3 Pin Assignments 9 C13 PF15/BREQ D12 PF14/BACK K1 PL13/IRQOUT K2 PL12/IRQ4 M3 PL7/SCK2 U10 PC3/RxD2 U12 PB15/PULS5/SCK2 W10 PC2/TxD2 Y12 PB13/SCK0 1.2 Block Diagram Figure 1.1 Block Diagram Figure amended Port SSCK1/PL7/SCK2 SCS0/PL12/IRQ4 SCS1/PL13/IRQOUT PA14/TxD0/SSO0 PA15/RxD0/SSI0 PB13/SCK0/SSCK0 PB15/PULS5/SCK2/SSCK1 PC2/TxD2/SSO1 PC3/RxD2/SSI1 XTAL Clock pulse generator Peripheral address bus (19 bits) 1.3.1 Pin Arrangement Figure 1.2 Pin Arrangement Pin name added 45 SCS0/PF14/BACK 46 SCS1/PF15/BREQ 143 PA14/TxD0/SSO0 144 PA15/RxD0/SSI0 160 PB13/SCK0/SSCK0 164 PB15/PULS5/SCK2/SSCK1 167 PC2/TxD2/SSO1 168 PC3/RxD2/SSI1 223 SSCK1/PL7/SCK2 230 SCS0/PL12/IRQ4 231 SCS1/PL13/IRQOUT Figure 1.3 Pin Arrangement (BP-272) Pin name added C13 PF15/BREQ/SCS1 D12 PF14/BACK/SCS0 K1 PL13/IRQOUT/SCS1 K2 PL12/IRQ4/SCS0 M3 PL7/SCK2/SSCK1 U10 PC3/RxD2/SSI1 U12 PB15/PULS5/SCK2/SSCK1 W10 PC2/TxD2/SSO1 Y12 PB13/SCK0/SSCK0 SH7058S/SH7059
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 1.3.2 Pin Functions Table 1.2 Pin Functions 11
Pin No. Type Clock Symbol XTAL FP-256H 53 BP-272 A15 I/O Input
Type Clock Symbol XTAL FP-256H 53
SH7058S/SH7059 1.3.2 Pin Functions Table 1.2 Pin Functions Table amended
Pin No. BP-272 A15 I/O Input/ output
Synchronous Serial Communication Unit (SSU) added SSO0, SSO1, SSI0, SSI1, SSCK0, SSCK1, SCS0, SCS1 1.3.3 Pin Assignments Table 1.3 Pin Assignments 20, 23, 24, 26
Pin No. FP-256H BP-272 33 34 45 46 143 144 160 164 167 168 223 230 231 C9 C10 D12 C13 Y17 Y16 Y12 U12 W10 U10 M3 K2 K1 MCU Mode PF4/A20 PF5/A21/POD PF14/BACK PF15/BREQ PA14/TxD0 PA15/RxD0 PB13/SCK0 PB15/PULS5/SCK2 PC2/TxD2 PC3/RxD2 PL7/SCK2 PL12/IRQ4 PL13/IRQOUT Programmer Mode NC NC NC Vcc NC NC NC NC NC NC NC OE NC
FP-256H 33 34 45 46 143 144 160 164 167 168 223 230 231
1.3.3 Pin Assignments Table 1.3 Pin Assignments Table amended
Pin No. BP-272 C9 C10 D12 C13 Y17 Y16 Y12 U12 W10 U10 M3 K2 K1 MCU Mode PF4/A20 PF5/A21/POD PF14/BACK/SCS0 PF15/BREQ/SCS1 PA14/TxD0/SSO0 PA15/RxD0/SSI0 PB13/SCK0/SSCK0 PB15/PULS5/SCK2/SSCK1 PC2/TxD2/SSO1 PC3/RxD2/SSI1 PL7/SCK2/SSCK1 PL12/IRQ4/SCS0 PL13/IRQOUT/SCS1 Programmer Mode A20 A21 NC Vcc NC NC NC NC NC NC NC OE NC
2.3.1 RISC-type Instruction Set One Instruction per Cycle: 35 The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 25 ns at 40 MHz.
2.3.1 RISC-type Instruction Set One Instruction per Cycle Description amended The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 12.5 ns at 80 MHz.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 2.5.1 State Transitions Figure 2.8 Transitions between Processing States 59
From any state when RES = 0 and HSTBY = 1 Power-on reset state
SH7058S/SH7059 2.5.1 State Transitions Figure 2.8 Transitions between Processing States Figure amended
From any state when RES = 0 and HSTBY = 1 Power-on reset state
RES = 0 HSTBY = 1
RES = 0 HSTBY = 1
NMI pin 0 1
RES = 1 When an interrupt source or DMA address error occurs Exception processing state When an interrupt source or DMA address error occurs
RES = 1
Exception processing state
Bus request cleared Bus request generated Bus release state Exception processing source occurs Bus request cleared
NMI interrupt source occurs Exception processing ends
Bus request cleared Bus request generated Bus release state Exception processing source occurs Bus request cleared Exception processing ends
Bus request generated Bus request generated Bus request cleared
Bus request generated Bus request generated SBY bit set for SLEEP instruction Bus request cleared
Program execution state
Program execution state SBY bit set for SLEEP instruction
SBY bit cleared for SLEEP instruction
SBY bit cleared for SLEEP instruction
Sleep mode
Software standby mode Hardware standby mode
Sleep mode
Software standby mode Hardware standby mode
Power-down state From any state when RES = 0 and HSTBY = 0
Power-down state From any state when RES = 0 and HSTBY = 0
Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state.
Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state.
5.1 Overview 73 The internal clock signal (), with frequency either four or eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules. 5.1.1 Block Diagram Figure 5.1 Block Diagram of Clock Pulse Generator 73
5.1 Overview Description amended The internal clock signal (), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules. 5.1.1 Block Diagram Figure 5.1 Block Diagram of Clock Pulse Generator Figure amended SYSCR1, Oscillation stop detection circuit, and On-chip oscillator circuit deleted
XTAL Oscillator circuit PLL multiplier circuit Internal clock () X 4 or X 8 5.1.2 Pin Configuration Table 5.1 CPG Pins 74
Pin Name Crystal Abbreviation XTAL I/O Input
XTAL Oscillator circuit PLL multiplier circuit Internal clock () X8 5.1.2 Pin Configuration Table 5.1 CPG Pins Table amended
Pin Name Crystal Abbreviation XTAL I/O Input/output
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 5.1.3 Related Register Table 5.2 CPG Register 74 5.2.1 Frequency Ranges Table 5.3 Input Frequency and Operating Frequency 75 SH7058S/SH7059 5.1.3 Related Register Table 5.2 CPG Register Deleted 5.2.1 Frequency Ranges Table 5.2 Input Frequency and Operating Frequency Table amended Description of x 4 version (PLL Multiplication Factor) deleted Description amended The internal clock signal (), with frequency either four or eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules such as CPU, FPU, and DMAC. Figure 5.2 Frequencies and Phases of Clock Signals The internal clock signal (), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules such as CPU, FPU, and DMAC. Figure 5.2 Frequencies and Phases of Clock Signals Figure amended Description of internal clock () = input clock x 4 deleted 5.2.2 Clock Selection 75,76 5.2.3 Notes on Register Access Figure 5.3 Writing to SYSCR2 76, 77 5.4 Oscillation Stop Detection Function 79 - 81 6.1.1Types of Exception Processing and Priority Table 6.1 Types of Exception Processing and Priority Order 85
Exception Source Interrupt On-chip peripheral modules: Serial communication interface (SCI) Controller area network 0 (HCAN0)
5.2.2 Clock Selection Deleted 5.2.3 Notes on Register Access Figure 5.3 Writing to SYSCR2 Deleted Deleted 6.1.1Types of Exception Processing and Priority Table 6.1 Types of Exception Processing and Priority Order On-chip peripheral modules: Synchronous serial communication unit (SSU) added
Exception Interrupt Source On-chip peripheral modules: Serial communication interface (SCI) Synchronous serial communication unit (SSU) Controller area network 0 (HCAN0)
6.2.2 Power-On Reset 90 Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 20 tcyc when the clock is running. In the power-on reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized. 6.4.1 Interrupt Sources Table 6.7 Interrupt Sources 93
6.2.2 Power-On Reset Description amended Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 10 tcyc when the clock is running. In the power-on reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized. 6.4.1 Interrupt Sources Table 6.7 Interrupt Sources Synchronous serial communication unit (SSU) added
Type On-chip peripheral module Request Source Synchronous communication unit (SSU) Number of Sources 6
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 7.1.2 Block Diagram Figure 7.1 INTC Block Diagram 102 7.2.5 On-Chip Peripheral Module Interrupts 105 7.2.6 Interrupt Exception Vectors and Priority Rankings Table 7.3 Interrupt Exception Processing Vectors and Priorities 113, 114 Interrupt Source
Interrupt Source SCI0 ERI0 RXI0 TXI0 SCI2 ERI2 RXI2 TXI2
SCI2/ SSU1*
SH7058S/SH7059 7.1.2 Block Diagram Figure 7.1 INTC Block Diagram SSU interrupt request added to CPU/DMAC request judgment 7.2.5 On-Chip Peripheral Module Interrupts Synchronous communication unit (SSU) added 7.2.6 Interrupt Exception Vectors and Priority Rankings Table 7.3 Interrupt Exception Processing Vectors and Priorities Interrupt Source: SSU added
Interrupt Source SCI0/ SSU0* ERI0/ SSERI0 RXI0/ SSRXI0 TXI0/ SSTSI0 ERI2/ SSERI1 RXI2/ SSRXI1 TXI2/ SSTSI1
7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) Table 7.4 Interrupt Request Sources and IPRA-IPRL 116
Bits Register Interrupt priority register K 15-12 SCI0 7-4 SCI2
7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) Table 7.4 Interrupt Request Sources and IPRA-IPRL Table amended
Bits Register Interrupt priority register K 15-12 SCI0/SSU0* 7-4 SCI2/SSU1*
7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) 116 If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0, A/D0, and MTAD0, and CMT1, A/D1, and MTAD1), those multiple modules are set to the same priority rank. IPRA-IPRL are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. 7.3.3 IRQ Status Register (ISR) 118 A reset and hardware standby mode initialize ISR but software standby mode does not.
7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) Description amended If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0, A/D0, and MTAD0, CMT1, A/D1, and MTAD1, SCI0 and SSU0*, and SCI2 and SSU1*), those multiple modules are set to the same priority rank. IPRA-IPRL are initialized to H'0000 by a reset, in hardware standby mode and in software standby mode. 7.3.3 IRQ Status Register (ISR) Description amended A reset, hardware standby mode and software standby mode initialize ISR .
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 7.5 Interrupt Response Time Table 7.5 Interrupt Response Time (Multiplication Ratio of 8) 122
Number of States Item Peripheral Module
Item Peripheral Module 0 or 6
SH7058S/SH7059 7.5 Interrupt Response Time Table 7.5 Interrupt Response Time Table amended
Number of States NMI 1 to 4 IRQ 6 to 9 Notes For the number of states required for each interrupt, see the note below.
NMI 1 to 4 [1 or 2]
IRQ 6 to 9 [3 to 5]
Notes For the number of states required for each interrupt, see the note (*) below. The values enclosed in [ ] are values for when the multiplication ratio is 4.
Synchronizing input signal 0 or 6 (synchronized with peripheral [0 or 3] clock P) with internal clock and DMAC activation judgment
Synchronizing input signal (synchronized with peripheral clock P ) with internal clock and DMAC activation judgment
8.2.1 User Break Address Register (UBAR) 128 UBARH and UBARL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. 8.2.2 User Break Address Mask Register (UBAMR) 129 UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. 8.2.3 User Break Bus Cycle Register (UBBR) 130 UBBR is initialized to H'0000 by a power on reset and in module standby mode. It is not initialized in software standby mode. 8.2.4 User Break Control Register (UBCR) 132 UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not initialized in software standby mode. Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0)
Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the UBCTRG signal output in the event of a condition match.
Bit 2: CKS1 0 Bit 1: CKS0 0 Description When the internal clock is four times an input clock, UBCTRG pulse width is /2 When the internal clock is eight times an input clock, UBCTRG pulse width is /4 (Initial value)
8.2.1 User Break Address Register (UBAR) Description amended UBARH and UBARL are initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. 8.2.2 User Break Address Mask Register (UBAMR) Description amended UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. 8.2.3 User Break Bus Cycle Register (UBBR) Description amended UBBR is initialized to H'0000 by a power on reset, in module standby mode, and in software standby mode. 8.2.4 User Break Control Register (UBCR) Description amended UBCR is initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode.
Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0)
Bit 2: CKS1 0 Bit 1: CKS0 0 Description UBCTRG pulse width is /4 (Initial value)
Notes: : Internal clock See section 8.5.7, Internal Clock () Multiplication Ratio and UBCTRG Pulse Width. 8.5.7 Internal Clock () Multiplication Ratio and UBCTRG Pulse Width 140 9.1.2 Block Diagram Figure 9.1 BSC Block Diagram 142
Notes: : Internal clock
8.5.7 Internal Clock () Multiplication Ratio and UBCTRG Pulse Width Deleted 9.1.2 Block Diagram Figure 9.1 BSC Block Diagram Bus arbitration control unit added
BREQ BACK Bus arbitration control unit
Rev.3.00 Mar. 12, 2008 Page xiv of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 9.1.4 Register configuration 143 All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware standby mode. Values are retained in a manual reset and in software standby mode. 9.1.5 Address Map Table 9.3 Address Map 145 SH7058S/SH7059 9.1.4 Register configuration Description amended All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware standby mode. Values are retained in a manual reset . 9.1.5 Address Map Table 9.3 Address Map (SH7058S) Table deleted * Number of Access Cycles for On-Chip Peripheral Module Registers
Table 9.4 Address Map (SH7059) Newly added Table 9.5 Number of Access Cycles for Peripheral Module registers Newly added 9.2.1 Bus Control Register 1 (BCR1) 146 BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 9.2.2 Bus Control Register 2 (BCR2) 148 BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 9.2.3 Wait Control Register (WCR) 151 WCR is initialized to H'7777 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 9.2.4 RAM Emulation Register (RAMER) 152 RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 9.2.1 Bus Control Register 1 (BCR1) Description amended BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode, and in software standby mode. It is not initialized by a manual reset . 9.2.2 Bus Control Register 2 (BCR2) Description amended BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode, and in software standby mode. It is not initialized by a manual reset . 9.2.3 Wait Control Register (WCR) Description amended WCR is initialized to H'7777 by a power-on reset and in hardware standby mode, and in software standby mode. It is not initialized by a manual reset . 9.2.4 RAM Emulation Register (RAMER) Description amended RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode, in software standby mode. It is not initialized by a manual reset . * SH7059 Newly added 10.1.2 Block Diagram Figure 10.1 DMAC Block Diagram 165 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) 172
Bit 20: RS4 0 1 1 1 Bit 19: RS3 1 0 1 1 Bit 18: RS2 1 0 1 1 Bit 17: RS1 1 0 0 1 Bit 16: RS0 0 0 1 0 Description No request* No request* No request* No request*
10.1.2 Block Diagram Figure 10.1 DMAC Block Diagram Figure amended SSU0*, SSU1* Request priority control 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) Table amended
Bit 20: RS4 0 1 1 1 Bit 19: RS3 1 0 1 1 Bit 18: RS2 1 0 1 1 Bit 17: RS1 1 0 0 1 Bit 16: RS0 0 0 1 0 Description SSU0 transmission* SSU0 reception* SSU1 transmission* SSU1 reception*
Rev.3.00 Mar. 12, 2008 Page xv of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 10.3.2 DMA Transfer Requests 179 - 182 On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters. When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. SH7058S/SH7059 10.3.2 DMA Transfer Requests Description amended On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters; the receiver data full interrupts (SSRXI), transmit data empty or transmit end interrupts (SSTSI) from two synchronous serial communication unit (SSU). When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. When the transfer request is set to RXI (transfer request because the SCI's receive data register is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI's transmit data register is empty), the transfer destination must be the SCI's transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data. If the transfer request by the receive data full of the SSU (SSRXI) is selected, the transfer destination must be the SS receive data register (SSRDR) of the SSU. If the transmit data empty or transmit end of the SSU (SSTSI) is selected, the transfer destination must be the SS transmit data register (SSTDR) of the SSU.
When the transfer request is set to RXI (transfer request because the SCI's receive data register is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI's transmit data register is empty), the transfer destination must be the SCI's transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data.
Rev.3.00 Mar. 12, 2008 Page xvi of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits 180, 181 SH7058S/SH7059 Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits Table and legend amended SSU0 transmit block, SSU0 receive block, SSU1 transmit block, and SSU1 receive block added. Legend:
DMAC Transfer Request Source SCI0 transmit block SCI0 receive block SCI1 transmit block SCI1 receive block SCI2 transmit block SCI2 receive block SCI3 transmit block SCI3 receive block SCI4 transmit block SCI4 receive block A/D0
Description of SSU0,SSU1 added
DMAC Transfer Request Signal TXI0 (SCI0 transmitdata-empty transfer request) RXI0 (SCI0 receivedata-full transfer request) TXI1 (SCI1 transmitdata-empty transfer request) RXI1 (SCI1 receivedata-full transfer request) TXI2 (SCI2 transmitdata-empty transfer request) RXI2 (SCI2 receivedata-full transfer request) TXI3 (SCI3 transmitdata-empty transfer request) RXI3 (SCI3 receivedata-full transfer request) TXI4 (SCI4 transmitdata-empty transfer request) RXI4 (SCI4 receivedata-full transfer request) ADI0 (A/D0 conversion end interrupt) ADI1 (A/D1 conversion end interrupt) ADI2 (A/D2 conversion end interrupt) RM0 (HCAN0 receive interrupt) Transfer Source Don't care* Transfer Destination TDR0 Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal
1 0 1 RS4 0 RS3 0 RS2 0 RS1 0 RS0 1 DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Don't care* Transfer Destination TDR0 Bus Mode Cycle-steal SCI0 transmit block TXI0 (SCI0 transmitdata-empty transfer request) SCI0 receive block
RS4 0
RS3 0
RS2 0
RS1 0
RS0 1
1
0 1
1
0
RDR0
Don't care*
RXI0 (SCI0 receive-data- RDR0 full transfer request) Don't care*
Don't care* TDR1
Cycle-steal Cycle-steal
SCI1 transmit block TXI1 (SCI1 transmitdata-empty transfer request) SCI1 receive block
1
Don't care*
TDR1
1
0
0 1
RXI1 (SCI1 receive-data- RDR1 full transfer request) Don't care*
Don't care* TDR2
Cycle-steal Cycle-steal
1
0
0
RDR1
Don't care*
SCI2 transmit block TXI2 (SCI2 transmitdata-empty transfer request) SCI2 receive block
RXI2 (SCI2 receive-data- RDR2 full transfer request) Don't care*
Don't care* TDR3
Cycle-steal Cycle-steal
1
Don't care*
TDR2
Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal
1 1 0 0
SCI3 transmit block TXI3 (SCI3 transmitdata-empty transfer request) SCI3 receive block
1
0
RDR2
Don't care*
0 1
RXI3 (SCI3 receive-data- RDR3 full transfer request) Don't care*
Don't care* TDR4
Cycle-steal Cycle-steal
1
Don't care*
TDR3
SCI4 transmit block TXI4 (SCI4 transmitdata-empty transfer request) SCI4 receive block A/D0 A/D1 A/D2
1
0 1
RXI4 (SCI4 receive-data- RDR4 full transfer request) ADI0 (A/D0 ADDR0- conversion end interrupt) ADDR11 ADI1 (A/D1 ADDR12- conversion end interrupt) ADDR23 ADI2 (A/D2 ADDR24- conversion end interrupt) ADDR31 Don't care*
Don't care* Don't care* Don't care* Don't care* SSTDR0_0 to SSTDR3_0
Cycle-steal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Cycle-steal
1
0
0
0
RDR3
Don't care*
1
0
0 1 0
1
Don't care*
TDR4
1
0
RDR4
Don't care*
Burst/cyclesteal
1
SSU0 transmit block SSTSI0 (transmitdata-empty or transmit-end transfer request of SSU0) HCAN0 RM0 (HCAN0 receive interrupt)
MB0-MB31 SSRDR0_0 to SSRDR3_0 Don't care* Don't care* Don't care* Don't care* Don't care*
Don't care* Don't care*
1
ADDR0- ADDR11 ADDR12- ADDR23 ADDR24- ADDR31 MB0-MB15
Don't care*
Burst/cyclesteal Burst/cyclesteal
Burst/cyclesteal Cycle-steal
1
0
0
0
0
1
0
0
A/D1
Don't care*
SSU0 receive block SSRXI0 (receive-datafull transfer request of SSU0) ATU-II ATU-II ATU-II ATU-II ATU-II ICI0A (ICR0A input capture generation) ICI0B (ICR0B input capture generation) ICI0C (ICR0C input capture generation) ICI0D (ICR0D input capture generation) CMI6A (CYLR6A compare-match generation)
1 1 0 1 1 0 0 1
Don't care* Don't care* Don't care* Don't care* Don't care*
Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal
1
A/D2
Don't care*
Burst/cyclesteal Burst/cyclesteal
1
1
HCAN0
Don't care*
RS4 1
RS3 0
RS2 0
RS1 0 1
RS0 1 0 1
DMAC Transfer Request Source ATU-II ATU-II ATU-II ATU-II ATU-II
DMAC Transfer Request Signal ICI0A (ICR0A input capture generation) ICI0B (ICR0B input capture generation) ICI0C (ICR0C input capture generation) ICI0D (ICR0D input capture generation) CMI6A (CYLR6A compare-match generation) CMI6B (CYLR6B compare-match generation) CMI6C (CYLR6C compare-match generation) CMI6D (CYLR6D compare-match generation) CMI7A (CYLR7A compare-match generation) CMI7B (CYLR7B compare-match generation) CMI7C (CYLR7C compare-match generation) CMI7D (CYLR7D compare-match generation)
Transfer Source Don't care* Don't care* Don't care* Don't care* Don't care*
Transfer Destination Don't care* Don't care* Don't care* Don't care* Don't care*
RS4
RS3 0
RS2 1
RS1 1
RS0 0
DMAC Transfer Request Source ATU-II
DMAC Transfer Request Signal CMI6B (CYLR6B compare-match generation) CMI6C (CYLR6C compare-match generation) CMI6D (CYLR6D compare-match generation) CMI7A (CYLR7A compare-match generation) CMI7B (CYLR7B compare-match generation) CMI7C (CYLR7C compare-match generation) CMI7D (CYLR7D compare-match generation)
Transfer Source Don't care*
Transfer Destination Don't care*
Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Cycle-steal
Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal
1
1
ATU-II
Don't care*
Don't care*
1
0
0
0
ATU-II
Don't care*
Don't care*
1
0
0 1
1
ATU-II
Don't care*
Don't care*
1
0
ATU-II
Don't care*
Don't care*
1
ATU-II
Don't care*
Don't care*
1
0
ATU-II
Don't care*
Don't care*
1
0
0
ATU-II
Don't care*
Don't care*
1
ATU-II
Don't care*
Don't care*
Burst/cyclesteal Burst/cyclesteal
1
1
1
0
0
0
ATU-II
Don't care*
Don't care*
SSU1 transmit block SSTSI1 (transmitdata-empty or transmit-end transfer request of SSU1) SSU1 receive block SSRXI1 (receive-datafull transfer request of SSU1)
Don't care*
SSTDR0_1 to SSTDR3_1
0
1
ATU-II
Don't care*
Don't care*
Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal
SSRDR0_1 to SSRDR3_1
Don't care*
Cycle-steal
1
0
ATU-II
Don't care*
Don't care*
1
ATU-II
Don't care*
Don't care*
1
0
0
ATU-II
Don't care*
Don't care*
Rev.3.00 Mar. 12, 2008 Page xvii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category 190 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the SCI, HCAN0, or A/D converter for the transfer request source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the SCI, HCAN0, or A/D converter, the transfer source or transfer destination must be same as the transfer source. 3. When the transfer request source is the SCI, only cycle-steal mode is possible. 11.1.1 Features Table 11.1 ATU-II Functions 202, 203
Item Counter configuration Clock sources Channel 0 -/32 Channel 1 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Channel 2 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Channels 3-5 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM
SH7058S/SH7059 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category Note amended 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the SCI, 5 HCAN0, SSU* , or A/D converter for the transfer request source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the 5 SCI, HCAN0, SSU* , or A/D converter, the transfer source or transfer destination must be same as the transfer source. 3. When the transfer request source is the SCI, or SSU* , only cycle-steal mode is possible. 11.1.1 Features Table 11.1 ATU-II Functions Table amended
Item Counter configuration Clock sources Channel 0 P-P/32 Channel 1 (P-P/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Channel 2 (P-P/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Channels 3-5 (P-P/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM
5
Item Counter configuration
Channels 6, 7 Clock sources (-/32) x (1/2n) (n = 0-5)
Channel 8 (-/32) x (1/2n) (n = 0-5)
Channel 9
Channel 10 (-/32)
Channels 11 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB
Item Counter configuration
Channels 6, 7 Clock sources (P-P/32) x (1/2n) (n = 0-5)
Channel 8 (P-P/32) x (1/2n) (n = 0-5)
Channel 9
Channel 10 (P-P/32)
Channels 11 (P-P/32) x (1/2n) (n = 0-5) TCLKA, TCLKB
11.1.6 Prescaler Diagram Figure 11.12 Prescaler Diagram 229 Input clock /2 11.2.5 Timer Status Registers (TSR) 273 * Bit 3--Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D input capture or compare-match.
11.1.6 Prescaler Diagram Figure 11.12 Prescaler Diagram Figure amended Input clock P 11.2.5 Timer Status Registers (TSR) Description amended * Bit 3--Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR3D input capture or compare-match.
11.3.9 PWM Timer Function Figure 11.21 PWM Timer Operation 375
P
11.3.9 PWM Timer Function Figure 11.21 PWM Timer Operation Figure amended
P
STR
STR6A
TCNT6A Clock
TCNT6A Clock
TCNT6A
0001
0002
0003
0004
0003
0002
0001
0000
0001
0002
0003
0004
0003
0002
0001
0000
0001
0002
0003
TCNT6A
0001
0002
0003
0004
0001
0002
0003
0004
0001
0002
0003
0004
0001
0002
0003
0004
0001
0002
0003
CYLR6A Data = 0000 Write to BFR6A
0004 Data = 0004 Data = 0001
CYLR6A Data = 0000 Write to BFR6A
0004 Data = 0004 Data = 0001
BFR6A
0002
0000
0004
0001
BFR6A
0002
0000
0004
0001
DTR6A
0002
0000
0004
0001
DTR6A
0002
0000
0004
0001
TO6A
* PWM output does not change for one cycle after activation
TO6A Cleared by software Cleared by software Cleared by software TSR6 CMF6A
* PWM output does not change for one cycle after activation
Cleared by software
Cleared by software
Cleared by software
TSR6 CMF6A Cycle Cycle Cycle Duty = 0% Cycle Duty = 100% Cycle
Cycle
Cycle
Cycle Duty = 0%
Cycle Duty = 100%
Cycle
Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation.
Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation.
Rev.3.00 Mar. 12, 2008 Page xviii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 11.3.11 Event Count Function and Event Cycle Measurement Figure 11.25 Event Cycle Measurement Operation SH7058S/SH7059 11.3.11 Event Count Function and Event Cycle Measurement Figure 11.25 Event Cycle Measurement Operation Figure amended
P
TCNT3 Clock
P
TCNT3 Clock
TCNT3 Compare-match trigger (from channel 9)
0000
0001
0002
0003
0004
0005
5678
5679
567A
567B
567C
567D
567E
TCNT3 Compare-match trigger (from channel 9)
0000
0001
0002
0003
0004
0005
5678
5679
567A
567B
567C
567D
567E
GR3A
0003
567A
GR3A
0004
567A
TSR3 IMF3A
Cleared by software
TSR3 IMF3A
Cleared by software
11.6 Sample Setup Procedures Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) 408 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify the output attribute. 11.7 Usage Notes 423 External Output Value in Software Standby Mode: In software standby mode, the ATU register and external output values are cleared to 0. However, while the channel 1, 2, and 11 TIO1A to TIO1H, TIO2A to TIO2H, TIO11A, and TIO11B external output values are cleared to 0 immediately after software standby mode is exited, other external output values and all registers are cleared to 0 immediately after a transition to software standby mode. Also, when pin output is inverted by the pin function controller's port B invert register (PBIR) or port K invert register (PKIR), the corresponding pins are set to 1. Figure 11.74 External Output Value Transition Points in Relation to Software Standby Mode 423 12.1.4 Register Configuration Table 12.2 Advanced Pulse Controller Register 429 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 12.2.1 Pulse Output Port Control Register (POPCR) 430 POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode.
11.6 Sample Setup Procedures Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) Description amended 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. .
11.7 Usage Notes Title and description amended External Output Values in Software Standby Mode and Pin State after Software Standby Mode Release: In software standby mode, the ATU register and external output values are initialized. The pin state is high impedance. Since the settings of the pin function controller (PFC) are initialized, the PFC must be set again to use the function of the ATU-II external pins after software standby release.
Figure 11.74 External Output Value Transition Points in Relation to Software Standby Mode Figure deleted 12.1.4 Register Configuration Table 12.2 Advanced Pulse Controller Register Note deleted
12.2.1 Pulse Output Port Control Register (POPCR) Description amended POPCR is initialized to H'0000 by a power-on reset, in hardware standby mode and in software standby mode.
Rev.3.00 Mar. 12, 2008 Page xix of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 13.2.2 Timer Control/Status Register (TCSR) 441 Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0)
Description Overflow Interval* ( = 40 MHz) 12.8 s 409.6 s 0.8 ms 1.6 ms 3.3 ms 6.6 ms 26.2 ms 52.4 ms
SH7058S/SH7059 13.2.2 Timer Control/Status Register (TCSR) Table amended Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0)
Description Overflow Interval* ( = 80 MHz) 6.4 s 204.8 s 409.6 s 0.8 ms 1.6 ms 3.3 ms 13.1 ms 26.2 ms
Note amended Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Refer to section 13.4.7, Multiplication Factor for Internal Clock Signal () and Overflow Time. 13.4.7 Multiplication Factor for Internal Clock Signal () and Overflow Time 449 14.1.3 Register Configuration Table 14.1 Register Configuration 453 Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles for byte access and word access, and eight or nine internal clock () cycles for longword access. * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags. 15.1.4 Register Configuration Table 15.2 Register 467 Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles for byte access and word access, and eight or nine internal clock () cycles for longword access. 1. Only 0 can be written to clear the flags. 2. Do not access empty addresses. 15.2.5 Serial Mode Register (SMR) 469 The CPU can always read and write to SMR. SMR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. 15.2.5 Serial Mode Register (SMR) Description amended The CPU can always read to SMR. The CPU should only perform write operations when making initial settings. Do not use the CPU to perform writes during transmit, receive, or transmit/receive operation. SMR is initialized to H'00 by a power-on reset, in hardware standby mode. The value is not retrained in software standby mode and it is initialized after release. It is not initialized by a manual reset. 15.1.4 Register Configuration Table 15.2 Register Note amended Notes: *1 Only 0 can be written to clear the flags. *2 Do not access empty addresses. Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. . 13.4.7 Multiplication Factor for Internal Clock Signal () and Overflow Time Deleted 14.1.3 Register Configuration Table 14.1 Register Configuration Note amended Notes: * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags.
Rev.3.00 Mar. 12, 2008 Page xx of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 15.2.6 Serial Control Register (SCR) 472 The CPU can always read and write to SCR. SCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. 15.2.8 Bit Rate Register (BRR) 480 The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Each channel has independent baud rate generator control, so different values can be set for each channel. SH7058S/SH7059 15.2.6 Serial Control Register (SCR) Description amended The CPU can always read/write to SCR. SCR is initialized to H'00 by a power-on reset and in hardware standby mode. The value is not retrained in software standby mode and it is initialized after release. It is not initialized by a manual reset. 15.2.8 Bit Rate Register (BRR) Description amended The CPU can always read to BRR. The CPU should only perform write operations when making initial settings. Do not use the CPU to perform writes during transmit, receive, or transmit/receive operation. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset . Each channel has independent baud rate generator control, so different values can be set for each channel. 15.2.9 Serial Direction Control Register (SDCR) Description amended The description in this section assumes LSB-first transfer. The CPU can always read from SDCR. The CPU should only write to SDCR when making initial settings. Do not use the CPU to write to SDCR during transmit, receive, or transmit/receive operation. SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset . 15.3.2 Operation in Asynchronous Mode SCI Initialization (Asynchronous Mode): Figure 15.5 Sample Flowchart for Transmitting Serial Data 494
Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC
15.2.9 Serial Direction Control Register (SDCR) 487 The description in this section assumes LSB-first transfer. SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. It is not initialized by a manual reset and in software standby mode.
15.3.2 Operation in Asynchronous Mode SCI Initialization (Asynchronous Mode): Figure 15.5 Sample Flowchart for Transmitting Serial Data Figure amended and note added
Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC
5
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 5. Receiving Serial Data (Asynchronous Mode): Figure 15.7 Sample Flowchart for Receiving Serial Data (1) 497
Clear RE bit in SCR to 0
Receiving Serial Data (Asynchronous Mode): Figure 15.7 Sample Flowchart for Receiving Serial Data (1) Figure amended and note added
Clear RE bit in SCR to 0 5
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5.
Rev.3.00 Mar. 12, 2008 Page xxi of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) Figure 15.8 Sample Flowchart for Receiving Serial Data (2) 498
Yes
SH7058S/SH7059 Figure 15.8 Sample Flowchart for Receiving Serial Data (2) Figure amended and note added
Yes
Break? No Framing error handling
Break? No
Clear RE bit in SCR to 0
Framing error handling
Clear RE bit in SCR to 0
5
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. 15.3.3 Multiprocessor Communication Transmitting Multiprocessor Serial Data: Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data 502
Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC
15.3.3 Multiprocessor Communication Transmitting Multiprocessor Serial Data: Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data Figure amended and note added
Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC
5
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 5. Receiving Multiprocessor Serial Data: Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) 504
Clear RE bit in SCR to 0
Receiving Multiprocessor Serial Data: Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Figure amended and note added
Clear RE bit in SCR to 0 6
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 6. Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) 505
No Framing error handling Clear RE bit in SCR to 0
Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Figure amended and note added
No Framing error handling Clear RE bit in SCR to 0 6
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 6.
Rev.3.00 Mar. 12, 2008 Page xxii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 15.3.4 Synchronous Operation Transmitting Serial Data (Synchronous Mode): Figure 15.18 Sample Flowchart for Serial Transmitting 509 SH7058S/SH7059 15.3.4 Synchronous Operation Transmitting Serial Data (Synchronous Mode): Figure 15.18 Sample Flowchart for Serial Transmitting Figure amended and note added
Clear TE bit to 0 in SCR
Clear TE bit to 0 in SCR
4
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 4. Receiving Serial Data (Synchronous Mode): Figure 15.20 Sample Flowchart for Serial Receiving (1) 511 Receiving Serial Data (Synchronous Mode): Figure 15.20 Sample Flowchart for Serial Receiving (1) Figure amended and note added
5
Clear RE bit in SCR to 0
Clear RE bit in SCR to 0
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.23 Sample Flowchart for Serial Transmission and Reception 514
Clear TE and RE bits in SCR to 0
Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.23 Sample Flowchart for Serial Transmission and Reception Figure amended and notes added
Clear TE and RE bits in SCR to 0 6
Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit/receive operation. However, this does not apply to operation 6. 15.5.10 Note on Writing to Registers During Transmit, Receive, and Transmit/Receive Operations Newly added Section 16 Synchronous Serial Communication Unit (SSU) Newly added 16.4.2 Master Control Register_n (MCR_n) (n = 0, 1) 545 Bit 5: MCR5 Important: Usage of sleep mode is limited. Be sure to carefully read section 16.8, Usage Notes. 16.4.3 General Status Register_n (GSR_n) (n = 0, 1) 550 Transmit/Receive Warning Flag Indicates an error warning. 0: Reset condition: When TEC < 96, REC < 96, or TEC 256 1: When 96 TEC < 256 or 96 REC 17.4.2 Master Control Register_n (MCR_n) (n = 0, 1) Description amended Bit 5: MCR5 Note: Do not access to MB during sleep mode. Certain restrictions apply when using sleep mode, Be sure to read section 17.8, Usage Notes. 17.4.3 General Status Register_n (GSR_n) (n = 0, 1) Description amended Transmit/Receive Warning Flag Indicates an error warning. 0: Reset condition: When TEC < 96, or REC < 96, or TEC 256 1: When 96 TEC < 256 or 96 REC Rev.3.00 Mar. 12, 2008 Page xxiii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 16.4.4 HCAN-II_Bit timing Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1) About Bit Configuration Register: 553 1-bit time (8-25 quanta) Table 16.5 TSEG1 and TSEG2 Settings 554 Note: *When BRP[7:0] = 0, TSEG2[2:0] 2 When BRP[7:0] 1, TSEG2[2:0] 1 16.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) * UMSR0n (n = 0, 1) 580 Indicate that an unread message has been overwritten for mailboxes 15 to 0. 16.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) 583
Bit: 15 14 13 12 11 10 9 8 7
TCR7
SH7058S/SH7059 17.4.4 HCAN II_ Bit Configuration Register n(HCAN II_BCR0_n,HCAN II_BCR1_n) (n = 0, 1) About Bit Configuration Register: Description amended 1-bit time (9-25 quanta) Table 17.5 TSEG1 and TSEG2 Settings Table and note amended Note: *When BPR [7:0] = H'00000000, TSEG [2:0] H'001 17.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) * UMSR0n (n = 0, 1) Table amended Indicate that an unread message has been overwritten or overrun for mailboxes 15 to 0. 17.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) Bit table amended
1 0
6
5
4
3
2
Bit: 15
TCR 15
14
TCR 14
13
TCR 13
12
TCR 12
11
TCR 11
10
TCR 10
9
TCR9
8
7
TCR7
6
5
4
3
2
1
0
TCR TCR TCR TCR TCR TCR TCR9 15 14 13 12 11 10
TPSC TPSC TPSC TPSC TPSC TPSC 5 4 3 2 1 0
TCR5 TCR4
TCR3 TCR2 TCR1 TCR0
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Initial Value:
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0
0 R/W
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: R/W
586
Bit 5 4 3 2 1 0 Bit Name TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial Value 0 0 0 0 0 0 R/W R/W R/W -- -- -- -- Description HCAN-II Timer Prescaler Divide the source clock (2 HCAN peripheral clock) before it is used for the timer. The following relationship exists between source clocks and the timer 000000: 1 source clock 000001: 2 source clock 000010: 4 source clock 000011: 6 source clock 000100: 8 source clock : 111111: 126 source clock
Table amended
Bit 5 4 3 2 1 0 Bit Name TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial Value 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description HCAN-II Timer Prescaler Divide the source clock (2 x P) before it is used for the timer. The following relationship exists between source clocks and the timer 000000: 1 x source clock 000001: 2 x source clock 000010: 4 x source clock 000011: 6 x source clock 000100: 8 x source clock : 111111: 126 x source clock
16.7.2 HCAN Settings Figure 16.7 Reset Sequence 598 Clear all mailboxes*
2
17.7.2 HCAN Settings Figure 17.7 Reset Sequence Figure amended Clear all mailboxes*
2
(MSG-control, data, timestamp, LAFM) 16.7.4 Message Transmission Cancellation Sequence Figure 16.10 Transmission Cancellation Sequence 602 Set ABACK[N] *
2
(MSG-control, data, timestamp, LAFM, Txtrigger) 17.7.4 Message Transmission Cancellation Sequence Figure 17.10 Transmission Cancellation Sequence Figure amended Set ABACK[N] Set TXACK[N]*
2
Set TXACK[N]
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 16.7.9 DMAC Interface Figure 16.13 DMAC Transfer Flowchart 608
Initial setting of DMAC Set activation source Set source and destination addresses Set number of transmissions and interrupts : Processing by hardware
SH7058S/SH7059 17.7.9 DMAC Interface Figure 17.13 DMAC Transfer Flowchart Figure amended
Initial setting of DMAC Set activation source Set source and destination addresses Set number of transmissions and interrupts : Processing by hardware
: Setting by user
: Setting by user
Receive a message at mailbox 0 in channel 0
Receive a message at mailbox 0 in channel 0
Activate DMAC
Activate DMAC
DMAC transfer ended?
DMAC transfer ended?
No
Yes
Set DMAC transfer end bit Clear RXPR and RFPR
Set DMAC transfer end bit Clear RXPR and RFPR
Enable DMAC interrupt
Enable DMAC interrupt
No
Yes
Interrupt to CPU
Interrupt to CPU
Clear DMAC interrupt flag
Clear DMAC interrupt flag
End
End
16.7.11 CAN Bus Interface Figure 16.16 High-Speed Interface Using HA13721 610 17.1.1 Features 617 * High-speed conversion Conversion time: minimum 13.3 s per channel (when peripheral clock (Pf) = 20 MHz) 17.1.4 Register Configuration Table 17.2 A/D Converter Registers 624 Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 1. A 16-bit access must be made on a word boundary. 2. Only 0 can be written to bit 7 to clear the flag. 17.4.3 Analog Input Sampling and A/D Conversion Time Table 17.4 A/D Conversion Time (Single Mode) 644 CKS0 : Peripheral Clock (P) = 10 to 20MHz CKS1 : Peripheral Clock (P) = 10MHz States (peripheral clock (P))
17.7.11 CAN Bus Interface Figure 17.16 Using the PCA82C250 in a High-Speed Interface Replaced due to the transceiver IC changed. 18.1.1 Features Description amended * High-speed conversion Conversion time: minimum 13.3 s per channel (when fop = 20 MHz) 18.1.4 Register Configuration Table 18.2 A/D Converter Registers Notes amended Notes: 1. A 16-bit access must be made on a word boundary. 2. Only 0 can be written to bit 7 to clear the flag. 18.4.3 Analog Input Sampling and A/D Conversion Time Table 18.4 A/D Conversion Time (Single Mode) Table amended CKS0 : fop = 10 to 20MHz CKS1 : fop = 10MHz States (CK base)
Rev.3.00 Mar. 12, 2008 Page xxv of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 17.6 Usage Notes 648 2. Relation between, AVSS, AVCC and VSS, VCC When using the A/D converter, set AVCC = 5.0 V 0.5 V, and AVSS = VSS. When the A/D converter is not used, set AVSS = VSS, and do not leave the AVCC pin open. 3. AVref input range Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVref AVCC when not used. If conditions above are not met, the reliability of the device may be adversely affected. 18.3 Interrupt Interface 18.4 PFC and I/O Port Interfaces 18.6 Appendices 19.1.4 Register Configuration Table 19.2 Register Configuration 697
2
SH7058S/SH7059 18.6 Usage Notes Description amended 2. Relation between, AVSS, AVCC and VSS, VCC When using the A/D converter, set AVCC = 5.0 V 0.5 V, and AVSS = VSS. When the A/D converter is not used, set AVSS = VSS, and the setting range is AVSS AVCC 5.5 V. 3. AVref input range Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVCC - 1.0 V AVref AVCC and AVSS AVref when not used. If conditions above are not met, the reliability of the device may be adversely affected. Deleted Deleted Deleted 20.1.4 Register Configuration Table 20.2 Register Configuration Table and note amended
Register Status register Abbreviation SDSR Initial Value*
2
Register Status register ID code register
Abbreviation SDSR SDIDR
Initial Value* H'0B01 H'001D200F
H'5001 (SH7058SF) H'0F01 (SH7059F)
ID code register
SDIDR
H'08016447 (SH7058SF) H'0800B447 (SH7059F)
Notes: 2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual) or in standby mode. 19.3.1 Instruction Register (SDIR) 699 SDIR can be initialized by the TRST signal, but is not initialized by a reset or in software standby mode.
Notes: 2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual) . 20.3.1 Instruction Register (SDIR) Description amended SDIR can be initialized by the TRST signal or in software standby mode, but is not initialized by a reset .
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 19.3.2 Status Register (SDSR) 701
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 1 R 10 -- 0 R 9 -- 1 R 8 -- 1 R Initial value: R/W:
SH7058S/SH7059 20.3.2 Status Register (SDSR) Description amended (SH7058SF)
Bit: 15 -- 0 R 14 -- 1 R 13 -- 0 R 12 -- 1 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R
(SH7059F)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 1 R 10 -- 1 R 9 -- 1 R 8 -- 1 R
SDSR is initialized by TRST signal input, but is not initialized by a reset or in software standby mode.
SDSR is initialized by TRST signal input or in software standby mode, but is not initialized by a reset . (SH7058SF)
Bits 15 to 1--Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should always be 0. Bit 11, 9, and 8 are always read as 1, and the write value should always be 1.
Bits 15, 13, and 11 to 1 are always read as 0, and the write value should always be 0. Bits 14 and 12 are always read as 1, and the write value should always be 1. (SH7059F) Bits 15 to 1--Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should always be 0. Bits 11 to 8 are always read as 1, and the write value should always be 1 Bit 0--Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is reaset by the TRST signal, but is not initialized by a reset . 20.3.3 Data Register (SDDR) Description amended This register is not initialized by a reset, signal. or by the TRST
Bit 0--Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is reset by the TRST signal , but is not initialized by a reset or in software standby mode. 19.3.3 Data Register (SDDR) 702 This register is not initialized by a reset, in hardware or software standby mode, or by the TRST signal.
Rev.3.00 Mar. 12, 2008 Page xxvii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 19.3.5 Boundary scan register (SDBSR) Table 19.5 Correspondence between Pins and Boundary Scan Register Bits 708, 710, 711, 713, 718
Pin No. 45 46 135 136 137 138 143 144 160 164 167 168 223 230 231 Pin Name PF14/BACK PF15/BREQ PA8/TIIO4A PA9/TIO4B PA10/TIO4C PA11/TIO4D PA14/TxD0 PA15/RxD0 PB13/SCK0 PB15/PULS5/ SCK2 PC2/TxD2 PC3/RxD2 PL7/SCK2 PL12/IRQ4 PL13/IRQOUT
SH7058S/SH7059 20.3.5 Boundary scan register (SDBSR) Table 20.5 Correspondence between Pins and Boundary Scan Register Bits Table amended
Pin No. 45 46 135 136 137 138 143 144 160 164 167 168 223 230 231 Pin Name PF14/BACK/SCS0 PF15/BREQ/SCS1 PA8/TIIO4A /ADTO0A PA9/TIO4B /ADTO0B PA10/TIO4C /ADTO1A PA11/TIO4D /ADTO1B PA14/TxD0 /SSO0 PA15/RxD0 /SSI0 PB13/SCK0 /SSCK0 PB15/PULS5/ SCK2/SSCK1 PC2/TxD2/SSO1 PC3/RxD2/SSI1 PL7/SCK2/SSCK1 PL12/IRQ4/SCS0 PL13/IRQOUT/SCS1
19.3.6 ID code register (SDIDR) 719 The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR can output H'001D200F, which is a fixed code, from TDO. However, no serial data can be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed.
20.3.6 ID code register (SDIDR) Description and table amended The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR outputs a fixed code via TDO. The codes are H'0802558 for the SH7058SF and H'0800B447 for the SH7059F. Serial data can not be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed. (SH7058SF)
Table
27 0001 0001 1101 12 11 0010 0000 0000 1 111
27 1000 0000 0001
12 0110
11 0100 0100
1 011
(SH7059F)
27 1000 0000 0000 12 1011 11 0100 0100 1 011
Rev.3.00 Mar. 12, 2008 Page xxviii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 19.4.3 H-UDI Reset 724 19.5.2 Notes on Use 725 20.2.1 Pin Descriptions Pin Functions in RAM Monitor Mode 733 Description of AUDCK pin The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 10 MHz. When no connection is made, this pin is pulled up internally. 20.3.2 Operation Figure 20.2 Example of Data Output (32-Bit Output) 734 20.4.3 H-UDI Reset Desciption added * In software standby mode 20.5.2 Notes on Use 5 to 10 added 21.2.1 Pin Descriptions Pin Functions in RAM Monitor Mode Description amended Description of AUDCK pin The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 1/8 of the internal operating frequency(). When no connection is made, this pin is pulled up internally. 21.3.2 Operation Figure 21.2 Example of Data Output (32-Bit Output)* Title amended and note added Note: * For details on the AUD reset timing and the timing in branch trace mode, refer to section 29.3.13, AUD timing. 20.4.3 Operation Figure 20.5 Example of Read Operation (Byte Read) Figure 20.6 Example of Write Operation (Longword Write) Figure 20.7 Example of Error Occurrence (Longword Read) 736,737 21.4.3 Operation Figure 21.5 Example of Read Operation (Byte Read)* Figure 21.6 Example of Write Operation (Longword Write)* Figure 21.7 Example of Error Occurrence (Longword Read)* Title amended and note added Note: * For details on the AUD reset timing and the timing in branch trace mode, refer to section 29.3.13, AUD timing. 20.5.1 Initialization 737 3. When AUDRST is driven low 4. When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 25.2.2) 5. When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 25.2.3) 20.5.2 Operation in Software Standby Mode 737 21.5.1 Initialization Description added and amended 3. In software standby mode 4. When AUDRST is driven low 5. When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 27.2.2) 6. When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 27.2.3) 21.5.2 Operation in Software Standby Mode Deleted SH7058S/SH7059
Rev.3.00 Mar. 12, 2008 Page xxix of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.1 Overview Table 21.1 SH7058 Multiplex Pins 739 - 741, 743
Function 1 (Related Module) PA14 input/output (port) PA15 input/output (port) PB13 input/output (port) PB15 input/output (port) PC2 input/output (port) PC3 input/output (port) PF14 input/output (port) PF15 input/output (port) PL7 input/output (port) PL12 input/output (port) PL13 input/output (port) Function 2 (Related Module) TxD0 output (SCI) RxD0 input (SCI) SCK0 input/output (SCI) PULS5 output (APC) TxD2 output (SCI) RxD2 input (SCI) BACK output (BSC) BREQ input (BSC) SCK2 input/output (SCI) IRQ4 input (INTC) IRQOUT output (INTC) IRQOUT output (INTC) SCK2 input/output (SCI) Function 3 (Related Module) Function 4 (Related Module)
SH7058S/SH7059 22.1 Overview Table 22.1 SH7059 Multiplex Pins Table amended
Function 1 (Related Module) PA14 input/output (port) PA15 input/output (port) PB13 input/output (port) PB15 input/output (port) PC2 input/output (port) PC3 input/output (port) PF14 input/output (port) PF15 input/output (port) PL7 input/output (port) PL12 input/output (port) PL13 input/output (port) Function 2 (Related Module) TxD0 output (SCI) RxD0 input (SCI) SCK0 input/output (SCI) PULS5 output (APC) TxD2 output (SCI) RxD2 input (SCI) BACK output (BSC) BREQ input (BSC) SCK2 input/output (SCI) IRQ4 input (INTC) IRQOUT output (INTC) Function 3 (Related Module) SSO0 output (SSU) SSI0 input (SSU) SSCK0 output (SSU) SCK2 input/output (SCI) SSO1 output (SSU) SSI1 input (SSU) SCS0 input/output (SSU) SCS1 input/output (SSU) SSCK1 output (SSU) SCS0 input/output (SSU) IRQOUT output (INTC) SCS1 input/output (SSU) SSCK1 output (SSU) Function 4 (Related Module)
21.3.1 Port A IO Register (PAIOR) 745 Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0) or ATU-II input/output pins, and disabled otherwise.
22.3.1 Port A IO Register (PAIOR) Description amended Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0), ATU-II input/output pins or transmit/receive input/output for the SSU (SSI0 and SSO0), and disabled otherwise. ...When port A pins function as PA15 to PA0, ATU-II input/output pins or transmit/receive input/output for the SSU (SSI0 and SSO0), a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.2 Port A Control Registers H and L (PACRH, PACRL) Description amended PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode.
...When port A pins function as PA15 to PA0 or ATU-II input/output pins, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.2 Port A Control Registers H and L (PACRH, PACRL) 746 PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) Port A Control Register H (PACRH) 746
Bit: 15 -- Initial value: R/W: 0 R 14 PA15MD 0 R/W 13 -- 0 R 12 PA14MD 0 R/W 8 PA12MD 0 R/W
Initial value: R/W:
SH7058S/SH7059 Port A Control Register H (PACRH) Description amended
Bit: 15 14 13 12 8 PA12MD 0 R/W PA15MD1 PA15MD0 PA14MD1 PA14MD0 0 R/W 0 R/W 0 R/W 0 R/W
* *
Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. Bit 14--PA15 Mode Bit (PA15MD): Selects the function of pin PA15/RxD0.
Description General input/output (PA15) Receive data input (RxD0) (Initial value)
*
Bits 15 and 14--PA15 Mode Bit 1,0 (PA15MD1, PA15MD0): Selects the function of pin PA15/RxD0/SSI0.
Bit 14: PA15MD0 0 1 Description General input/output (PA15) Receive data input (RxD0) Receive data input (SSI0) Received (Do not set) (Initial value)
Bit 15: PA15MD1 0
Bit 14: PA15MD 0 1
1
0 1
* *
Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. Bit 12--PA14 Mode Bit (PA14MD): Selects the function of pin PA14/TxD0.
Description General input/output (PA14) Transmit data output (TxD0) (Initial value)
*
Bits 13 and 12--PA14 Mode Bit 1,0 (PA14MD1, PA14MD0): Selects the function of pin PA14/TxD0/SSO0.
Bit 12: PA14MD0 0 1 Description General input/output (PA14) Transmit data output (TxD0) Transmit data output (SSO0) Received (Do not set) (Initial value)
Bit 13: PA14MD1 0
Bit 12: PA14MD 0 1
1
0 1
21.3.3 Port B IO Register (PBIOR) 750 Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode.
22.3.3 Port B IO Register (PBIOR) Description amended Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2, SSCK0, SSCK1), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, SCK2, SSCK0, and SSCK1, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.3.4 Port B Control Registers H and L (PBCRH, PBCRL) 751, 752 PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port B Control Register H (PBCRH)
Bit: 15 PB15 MD1 Initial value: R/W: 0 R/W 11 -- 0 R 10 PB13 MD 0 R/W Initial value: R/W:
SH7058S/SH7059 22.3.4 Port B Control Registers H and L (PBCRH, PBCRL) Description amended PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode and in software standby mode. They are not initialized in sleep mode. Port B Control Register H (PBCRH)
Bit: 15 PB15 MD1 0 R/W 11 PB13 MD1 0 R/W 10 PB13 MD0 0 R/W
*
Bits 15 and 14--PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2.
Bit 14: PB15MD0 1 Description Reserved (Do not set)
*
Bits 15 and 14--PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2/SSCK1.
Bit 14: PB15MD0 1 Description Serial clock output (SSCK1)
Bit 15: PB15MD1 1
Bit 15: PB15MD1 1
* *
Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. Bit 10--PB13 Mode Bit (PB13MD): Selects the function of pin PB13/SCK0.
Description General input/output (PB13) Serial clock input/output (SCK0) (Initial value)
*
Bits 11 and 10--PB13 Mode Bit 1,0 (PB13MD1, PB13MD0): Selects the function of pin PB13/SCK0/SSCK0.
Bit 10: PB13MD0 0 1 Description General input/output (PB13) Serial clock input/output (SCK0) Serial clock output (SSCK0) Reserved (Do not set) (Initial value)
Bit 11: PB13MD1
Bit 10: PB13MD 0 1
0
1
0 1
21.3.5 Port B Invert Register (PBIR) 756 Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2 to PB13/SCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU-II outputs or serial clock pins, and disabled otherwise. ...PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode.
22.3.5 Port B Invert Register (PBIR) Description amended Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB13/SCK0/SSCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU-II outputs or serial clock pins, and disabled otherwise. ...PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.3.6 Port C IO Register (PCIOR) 757 PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0), and disabled otherwise. When port C pins function as PC4 to PC0, a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. SH7058S/SH7059 22.3.6 Port C IO Register (PCIOR) Description amended PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0 or transmit/receive input/output for the SSU (SSI1 and SSO1)), and disabled otherwise. When port C pins function as PC4 to PC0 or transmit/receive input/output for the SSU (SSI1 and SSO1), a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.7 Port C Control Register (PCCR) Bit table amended
Bit: 7 -- Initial value: R/W: 0 R 6 PC3MD 0 R/W 5 -- 0 R 4 PC2MD 0 R/W 0 PC0MD 0 R/W Initial value: R/W: Bit: 7 6 5 4 0 PC0MD 0 R/W PC3MD1 PC3MD0 PC2MD1 PC2MD0 0 R/W 0 R/W 0 R/W 0 R/W
21.3.7 Port C Control Register (PCCR) 758
Description amended PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. * * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Bit 6--PC3 Mode Bit (PC3MD): Selects the function of pin PC3/RxD2.
Description General input/output (PC3) Receive data input (RxD2) (Initial value)
PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and software standby mode. It is not initialized in . sleep mode. * Bits 7 and 6--PC3 Mode Bit 1, 0 (PC3MD1, PC3MD0): Selects the function of pin PC3/RxD2/SSI1.
Bit 6: PC3MD0 0 1 1 0 1 Description General input/output (PC3) Receive data input (RxD2) Receive data input (SSI1) Reserved (Do not set) (Initial value)
Bit 7: PC3MD1 0
Bit 6: PC3MD 0 1
* *
Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. Bit 4--PC2 Mode Bit (PC2MD): Selects the function of pin PC2/TxD2.
Description General input/output (PC2) Transmit data output (TxD2) (Initial value)
*
Bits 5 and 4--PC2 Mode Bit 1,0 (PC2MD1, PC2MD0): Selects the function of pin PC2/TxD2/SSO1.
Bit 4: PC2MD0 0 1 Description General input/output (PC2) Transmit data output (TxD2) Transmit data output (SSO1) Reserved (Do not set) (Initial value)
Bit 5: PC2MD1 0
1
0 1
Bit 4: PC2MD 0 1
21.3.8 Port D IO Register (PDIOR) 759 PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode.
22.3.8 Port D IO Register (PDIOR) Description amended PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized . sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.3.9 Port D Control Registers H and L (PDCRH, PDCRL) 760 PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. 21.3.10 Port E IO Register (PEIOR) 764 PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.11 Port E Control Register (PECR) 765 PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.12 Port F IO Register (PFIOR) 770 Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ to PF0/A16. ... PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. SH7058S/SH7059 22.3.9 Port D Control Registers H and L (PDCRH, PDCRL) Description amended PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. 22.3.10 Port E IO Register (PEIOR) Description amended PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.11 Port E Control Register (PECR) Description amended PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.12 Port F IO Register (PFIOR) Description amended Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ/SCS1 to PF0/A16. ... PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. It is not initialized by a WDT power-on reset.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.3.13 Port F Control Registers H and L (PFCRH, PFCRL) 771, 772 PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode.
Bit: 15 14 13 -- 0 R 12 PF14MD 0 R/W 11 -- 0 R 8 PF12MD 0 R/W
Initial value: R/W:
SH7058S/SH7059 22.3.13 Port F Control Registers H and L (PFCRH, PFCRL) Description amended PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode.
Bit: 15 14 13 12 11 8 PF12MD 0 R/W CKHIZ PF15MD PF15MD PF14MD PF14MD 0 1 0 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
CKHIZ PF15MD Initial value: R/W: 0 R/W 0 R/W
*
Bit 14--PF15 Mode Bit (PF15MD): Selects the function of pin PF15/BREQ.
Description Expanded Mode General input/output (PF15) (Initial value) Bus request input (BREQ ) Single-Chip Mode General input/output (PF15) (Initial value) General input/output (PF15)
*
Bit 14: PF15MD 0 1
Bits 14 and 13--PF15 Mode Bit 0, 1 (PF15MD0, PF15MD1): Selects the function of pin PF15/BREQ/SCS1.
Description Bit 13: PF15MD1 0 1 Expanded Mode General input/output (PF15) (Initial value) Reserved (Do not set) Bus request input (BREQ) Reserved (Do not set) Single-Chip Mode General input/output (PF15) (Initial value) Chip select input/output (SCS1) General input/output (PF15)
Bit 14: PF15MD0 0
1
0 1
* *
Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. Bit 12--PF14 Mode Bit (PF14MD): Selects the function of pin PF14/BACK.
Description Expanded Mode General input/output (PF14) (Initial value) Bus acknowledge output (BACK) Single-Chip Mode General input/output (PF14) (Initial value) General input/output (PF14)
1 Bit 12: PF14MD0 0 Bit 11: PF14MD1 0 1 0 1 Expanded Mode General input/output (PF14) (Initial value) Reserved (Do not set) Bus acknowledge output (BACK) Reserved (Do not set)
*
Bits 12 and 11--PF14 Mode Bit 0,1(PF14MD0, PF14MD1): Selects the function of pin PF14/BACK/SCS0.
Description Single-Chip Mode General input/output (PF14) (Initial value) Chip select input/output (SCS0) General input/output (PF14)
Bit 12: PF14MD 0 1
*
Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. 22.3.14 Port G IO Register (PGIOR) Description amended PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, in software standby mode. It is not initialized in . sleep mode. 22.3.15 Port G Control Register (PGCR) Description amended PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode.
21.3.14 Port G IO Register (PGIOR) 776 PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.15 Port G Control Register (PGCR) 777 PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.3.16 Port H IO Register (PHIOR) 778 PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.17 Port H Control Register (PHCR) 779 PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.18 Port J IO Register (PJIOR) 785 PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.19 Port J Control Registers H and L (PJCRH, PJCRL) 786 PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. 21.3.20 Port K IO Register (PKIOR) 790 PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.21 Port K Control Registers H and L (PKCRH, PKCRL) 790 PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. 21.3.22 Port K Invert Register (PKIR) 795 PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. SH7058S/SH7059 22.3.16 Port H IO Register (PHIOR) Description amended PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.17 Port H Control Register (PHCR) Description amended PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.18 Port J IO Register (PJIOR) Description amended PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.19 Port J Control Registers H and L (PJCRH, PJCRL) Description amended PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. 22.3.20 Port K IO Register (PKIOR) Description amended PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.21 Port K Control Registers H and L (PKCRH, PKCRL) Description amended PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. 22.3.22 Port K Invert Register (PKIR) Description amended PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 21.3.23 Port L IO Register (PLIOR) 796 Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT to PL0/TI10. PLIOR is enabled when port L pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3, SCK4), and disabled otherwise. When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, and SCK4, a pin becomes an output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0. PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 21.3.24 Port L Control Registers H and L (PLCRH, PLCRL) Port L Control Register H (PLCRH) 797, 798 PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode.
Bit: 15 -- Initial value: R/W: 0 R 9 -- 0 R 8 PL12 MD 0 R/W Initial value: R/W:
SH7058S/SH7059 22.3.23 Port L IO Register (PLIOR) Description amended Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. PLIOR is enabled when port L pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3, SCK4, SSCK1), and disabled otherwise. When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, SCK4, and SSCK1 a pin becomes an output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0. PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.24 Port L Control Registers H and L (PLCRH, PLCRL) Port L Control Register H (PLCRH) Description amended PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode.
Bit: 15 -- 0 R 9 PL12 MD1 0 R/W 8 PL12 MD0 0 R/W
*
Bits 11 and 10--PL13 Mode Bits 1 and 0 (PL13MD1, PL13MD0): These bits select the function of pin PL13/IRQOUT.
Bit 10: PL13MD0 0 1 Description General input/output (PL13) IRQOUT is fixed high (IRQOUT) IRQOUT is output by INTC interrupt request (IRQOUT) Reserved (Do not set) (Initial value)
*
Bits 11 and 10--PL13 Mode Bits 1 and 0 (PL13MD1, PL13MD0): These bits select the function of pin PL13/IRQOUT/SCS1.
Bit 10: PL13MD0 0 1 Description General input/output (PL13) IRQOUT is fixed high (IRQOUT) IRQOUT is output by INTC interrupt request (IRQOUT) Chip select input/output (SCS1) (Initial value)
Bit 11: PL13MD1 0
Bit 11: PL13MD1 0
1
0 1
1
0 1
* *
Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. Bit 8--PL12 Mode Bit (PL12MD): Selects the function of pin PL12/IRQ4.
Description General input/output (PL12) Interrupt request input (IRQ4) (Initial value)
*
Bit 9, 8--PL12 Mode Bit 1,0 (PL12MD0,PL12MD0): Selects the function of pin PL12/IRQ4/SCS0.
Bit 8: PL12MD0 0 1 Description General input/output (PL12) Interrupt request input (IRQ4) Chip select input/output (SCS0) Reserved (Do not set) (Initial value)
Bit 9: PL12MD1 0
1
0 1
Bit 8: PL12MD 0 1
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) Port L Control Register L (PLCRL) 799
Bit: 15 -- Initial value: R/W: 0 R 14 PL7MD 0 R/W 8 PL4MD 0 R/W Initial value: R/W:
SH7058S/SH7059 Port L Control Register L (PLCRL) Description amended
Bit: 15 14 8 PL4MD 0 R/W
PL7MD1 PL7MD0 0 R/W 0 R/W
* *
Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. Bit 14--PL7 Mode Bit (PL7MD): Selects the function of pin PL7/SCK2.
Description General input/output (PL7) Serial clock input/output (SCK2) (Initial value)
*
Bits 15 and 14--PL7 Mode Bit 1, 0 (PL7MD1, PL7MD0): Selects the function of pin PL7/SCK2/SSCK1.
Bit 14: PL7MD0 0 1 Description General input/output (PL7) Serial clock input/output (SCK2) Serial clock output (SSCK1) Reserved (Do not set) (Initial value)
Bit 14: PL7MD 0 1
Bit 15: PL7MD1 0
1
0 1
21.3.25 Port L Invert Register (PLIR) 801 Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2. PLIR is enabled when port L pins function as serial clock pins, and disabled otherwise. ...PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode 22.2 Port A Figure 22.1 Port A 803
PA15 (I/O) / RxD0 (input) PA14 (I/O) / TxD0 (output)
22.3.25 Port L Invert Register (PLIR) Description amended Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2/SCK1. PLIR is enabled when port L pins function as serial clock pins, and disabled otherwise. ...PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.2 Port A Figure 23.1 Port A Figure amended
PA15 (I/O) / RxD0 (input) / SSI0 (input) PA14 (I/O) / TxD0 (output) / SSO0 (output)
22.2.1 Register Configuration Table 22.1 Register Configuration 804 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.2.2 Port A Data Register (PADR) 804 Bits PA15DR to PA0DR correspond to pins PA15/RxD0 to PA0/TI0A. ...PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.2.3 Port A Port Register (PAPR) 805 Bits PA15PR to PA0PR correspond to pins PA15/RxD0 to PA0/TI0A.
23.2.1 Register Configuration Table 23.1 Register Configuration Note deleted
23.2.2 Port A Data Register (PADR) Description amended Bits PA15DR to PA0DR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. ...PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.2.3 Port A Port Register (PAPR) Description amended Bits PA15PR to PA0PR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 22.3 Port B Figure 22.2 Port B 806
PB15 (I/O) / PULS5 (output) / SCK2 (I/O) PB13 (I/O) / SCK0 (I/O)
SH7058S/SH7059 23.3 Port B Figure 23.2 Port B Figure amended
PB15 (I/O) / PULS5 (output) / SCK2 (I/O) / SSCK1 (output) PB13 (I/O) / SCK0 (I/O) / SSCK0 (output)
22.3.1 Register Configuration Table 22.3 Register Configuration 806 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.3.2 Port B Data Register (PBDR) 807 Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. ...PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.3.3 Port B Port Register (PBPR) 808 Bits PB15PR to PB0PR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. 22.4 Port C Figure 22.3 Port C 808
PC3 (I/O) / RxD2 (input) PC2 (I/O) / TxD2 (output)
23.3.1 Register Configuration Table 23.3 Register Configuration Note deleted
23.3.2 Port B Data Register (PBDR) Description amended Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. ...PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.3.3 Port B Port Register (PBPR) Description amended Bits PB15PR to PB0PR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. 23.4 Port C Figure 23.3 Port C Figure amended
PC3 (I/O) / RxD2 (input) / SSI1 (input) PC2 (I/O) / TxD2 (output) / SSO1 (output)
22.4.1 Register Configuration Table 22.5 Register Configuration 808 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.4.2 Port C Data Register (PCDR) 809 PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.5.1 Register Configuration Table 22.7 Register Configuration 810 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles.
23.4.1 Register Configuration Table 23.5 Register Configuration Note deleted
23.4.2 Port C Data Register (PCDR) Description amended PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.5.1 Register Configuration Table 23.7 Register Configuration Note deleted
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 22.5.2 Port D Data Register (PDDR) 811 PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.6.1 Register Configuration Table 22.9 Register Configuration 813 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.6.2 Port E Data Register (PEDR) 814 PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.7 Port F Figure 22.6 Port F 816 Single-chip mode
PF15 (I/O) PF14 (I/O)
SH7058S/SH7059 23.5.2 Port D Data Register (PDDR) Description amended PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.6.1 Register Configuration Table 23.9 Register Configuration Note deleted
23.6.2 Port E Data Register (PEDR) Description amended PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.7 Port F Figure 23.6 Port F Figure amended Single-chip mode
PF15 (I/O) / SCS1 (I/O) PF14 (I/O) / SCS0 (I/O)
22.7.1 Register Configuration Table 22.11 Register Configuration 816 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.7.2 Port F Data Register (PFDR) 817 Bits PF15DR to PF0DR correspond to pins PF15/BREQ to PF0/A16. ... PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.8.1 Register Configuration Table 22.13 Register Configuration 819 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.8.2 Port G Data Register (PGDR) 819 PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode.
23.7.1 Register Configuration Table 23.11 Register Configuration Note deleted
23.7.2 Port F Data Register (PFDR) Description amended Bits PF15DR to PF0DR correspond to pins PF15/BREQ/SCS1 to PF0/A16. ... PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.8.1 Register Configuration Table 23.13 Register Configuration Note deleted
23.8.2 Port G Data Register (PGDR) Description amended PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 22.9.1 Register Configuration Table 22.15 Register Configuration 822 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.9.2 Port H Data Register (PHDR) 822 PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.10.1 Register Configuration Table 22.17 Register Configuration 824 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.10.2 Port J Data Register (PJDR) 824 PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.11.1 Register Configuration Table 22.19 Register Configuration 826 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.11.2 Port K Data Register (PKDR) 827 PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 22.12 Port L Figure 22.11 Port L 828
PL13 (I/O) / IRQOUT (output) PL12 (I/O) / IRQ4 (input) PL7 (I/O) / SCK2 (I/O)
SH7058S/SH7059 23.9.1 Register Configuration Table 23.15 Register Configuration Note deleted
23.9.2 Port H Data Register (PHDR) Description amended PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.10.1 Register Configuration Table 23.17 Register Configuration Note deleted
23.10.2 Port J Data Register (PJDR) Description amended PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.11.1 Register Configuration Table 23.19 Register Configuration Note deleted
23.11.2 Port K Data Register (PKDR) Description amended PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.12 Port L Figure 23.11 Port L Pin name added
PL13 (I/O) / IRQOUT (output) / SCS1 (I/O) PL12 (I/O) / IRQ4 (input) / SCS0 (I/O) PL7 (I/O) / SCK2 (I/O) / SSCK1 (output)
22.12.1 Register Configuration Table 22.21 Register Configuration 828 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles.
23.12.1 Register Configuration Table 23.21 Register Configuration Note deleted
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 22.12.2 Port L Data Register (PLDR) 829 Bits PL13DR to PL0DR correspond to pins PL13/IRQOUT to PL0/TI10. ... PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 23.1 Features 833, 834 * Two flash-memory MATs according to LSI initiation mode The user boot MAT is initiated at a power-on reset in user boot mode: 8 kbytes * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 40 MHz. 23.2.1 Block Diagram Figure 23.1 Block Diagram of Flash Memory 835 Memory MAT unit User boot MAT : 8 kbytes 23.2.4 Flash Memory Configuration Figure 23.3 Flash Memory Configuration 839 This LSI's flash memory is configured by the 1-Mbyte user MAT and 8-kbyte user boot MAT. SH7058S/SH7059 23.12.2 Port L Data Register (PLDR) Description amended Bits PL13DR to PL0DR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. ... PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 24.1 Features Description amended * Two flash-memory MATs according to LSI initiation mode The user boot MAT is initiated at a power-on reset in user boot mode: 12 Kbytes * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 80 MHz. 24.2.1 Block Diagram Figure 24.1 Block Diagram of Flash Memory Figure amended Memory MAT unit User boot MAT : 12 Kbytes 24.2.4 Flash Memory Configuration Figure 24.3 Flash Memory Configuration Description amended This LSI's flash memory is configured by the 1-Mbyte user MAT and 12-Kbyte user boot MAT. Figure amended Address H'00,0000 to H'00,1FFF 8 kbytes Address H'00,0000 to H'00,2FFF 12 Kbytes Description amended The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 8 kbytes or more. When a user boot MAT exceeding 8 kbytes is read from, an undefined value is read. The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 12 Kbytes or more. When a user boot MAT exceeding 12 Kbytes is read from, an undefined value is read.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 23.4.2 Programming/Erasing Interface Registers 847 The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. Except for the FLER bit in FCCS and FMATS, these registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. The FLER bit or FMATS is not initialized in software standby mode. * Bit 0--Source Program Copy Operation (SCO): ... Four NOP instructions must be executed immediately after setting this bit to 1. 23.4.3 Programming/Erasing Interface Parameters 851 ... This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset or in hardware standby mode. (1) Download Control 852 ... The on-chip RAM area to be downloaded is the area as much as 2 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 23.10. 23.4.4 RAM Emulation Register (RAMER) 862 ... RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode and is not initialized in software standby mode. The RAMER setting must be executed in user mode or in user program mode. 23.5.1 Boot Mode 864 ...After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. SH7058S/SH7059 24.4.2 Programming/Erasing Interface Registers Descritpion amended The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. These regiseters are initialized at a power-on reset, in hardware standby mode, or in software standby mode.
* Bit 0--Source Program Copy Operation (SCO): ... Eight NOP instructions must be executed immediately after setting this bit to 1. 24.4.3 Programming/Erasing Interface Parameters Description amended ... This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset, in hardware standby mode, or in software standby mode. (1) Download Control Description amended ...The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 24.10. 24.4.4 RAM Emulation Register (RAMER) Description amended ... RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode, or in software standby mode. The RAMER setting must be executed in user mode or in user program mode. 24.5.1 Boot Mode Description added ... After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The RAM areas used by boot mode are 3 Kbytes starting at address H'FFFF0000, 4 Kbytes starting at address H'FFFFB000, and 128 bytes from H'FFFFBF80 to H'FFFFBFFF, which are used as the stack. (1) SCI Interface Setting by Host Table 24.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Table amended
(1) SCI Interface Setting by Host Table 23.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI 865
Host Bit Rate 9,600 bps 19,200 bps System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 20 to 40 MHz (input frequency of 5 to 10 MHz) 20 to 40 MHz (input frequency of 5 to 10 MHz)
Host Bit Rate 9,600 bps 19,200 bps
System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 40 to 80 MHz (input frequency of 5 to 10 MHz) 40 to 80 MHz (input frequency of 5 to 10 MHz)
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 23.5.2 User Program Mode (1) On-Chip RAM Address Map when Programming/Erasing is Executed Figure 23.10 RAM Map after Download 869 Area to be downloaded (Size: 2 kbytes) Address FTDAR setting+2048 (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. 871 When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. (4) Erasing and Programming Procedure in User Program Mode Figure 23.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) 877 Set FTDAR to H'03 (Specify H'FFFF1800 as download destination) SH7058S/SH7059 24.5.2 User Program Mode (1) On-Chip RAM Address Map when Programming/Erasing is Executed Figure 24.10 RAM Map after Download Figure amended Area to be downloaded (Size: 3 Kbytes) Address FTDAR setting+3072 (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. Description amended When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Eight NOP instructions are executed immediately after the instructions that set the SCO bit to 1. (4) Erasing and Programming Procedure in User Program Mode Figure 24.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) Figure amended Set FTDAR to H'04 (Specify H'FFFF2000 as download destination) Description amended * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF1020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF1820 in this example). 23.5.3 User Boot Mode (1) User Boot Mode Initiation 878 ... When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 1.2 kbytes from H'FFFF0800 and 4 bytes from H'FFFFBFFC (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 40 MHz. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF1020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF2020 in this example). 24.5.3 User Boot Mode (1) User Boot Mode Initiation Description amended ... When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 3 Kbytes from H'FFFFB000 and 128 bytes from H'FFFFBF80 to H'FFFFBFFF (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 80 MHz.
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 23.6.1 Hardware Protection 881 Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. 23.6.3 Error Protection Figure 23.16 Transitions to and from Error Protection State 883, 884 * When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) When a SLEEP instruction (including software standby mode) is executed during programming/erasing SH7058S/SH7059 24.6.1 Hardware Protection Description amended Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state by the FWE pin, the downloading of an on-chip program and initialization of the flash memory are possible. 24.6.3 Error Protection Figure 24.16 Transitions to and from Error Protection State Description amended * * Flash memory is read during programming/erasing (including a vector read or an instruction fetch) When a SLEEP instruction programming/erasing is executed during
*
...Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s.
...Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Figure amended
Program mode Erase mode
Read disabled Programming/erasing enabled FLER=0
RES = 0 or HSTBY = 0
Reset or standby (Hardware protection)
Read enabled Programming/erasing disabled
Program mode Erase mode
Read disabled Programming/erasing enabled FLER=0
RES = 0 or HSTBY = 0
Reset or standby (Hardware protection)
Read enabled Programming/erasing disabled
Er
Error occurred
FLER=0 or =0 0 (S curr ES Y= Programming/erasing interface oft ed R TB register is in its initial state. wa HS RES=0 or re sta HSTBY=0 nd by )
ror
Er
oc
Error occurred
FLER=0 or =0 0 (S curr ES Y= Programming/erasing interface oft ed R TB register is in its initial state. wa HS RES=0 , re sta HSTBY=0 nd by or software standby mode cancellation )
ror
oc
Error protection mode
Read enabled Programming/erasing disabled FLER=1
Software standby mode
Error protection mode (Software standby)
Error protection mode
Read enabled Programming/erasing disabled FLER=1
Software standby mode
(Software standby)
Read disabled Programming/erasing disabled FLER=undefined
The power is not supplied in this LSI.
Read disabled Cancel Programming/erasing disabled software standby mode FLER=1
Programming/erasing interface register is in its initial state.
23.7 Flash Memory Emulation in RAM Figure 23.18 Example of Overlapped RAM Operation 886 EB0 to EB15 H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 ... H'FFFFF
24.7 Flash Memory Emulation in RAM Figure 24.18 Example of Overlapped RAM Operation Address amended EB0 to EB15 H'000000 H'001000 H'002000 H'003000 H'004000 H'005000 H'006000 H'007000 H'008000 ... H'0FFFFF
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) Figure 23.19 Programming of Tuned Data 887 EB0 to EB15 H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 ... H'FFFFF 23.8.1 Switching between User MAT and User Boot MAT 888 (2) To ensure that the MAT that has been switched to is accessible, execute four NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 8-kbyte memory space. If access goes beyond the 8-kbyte space, the values read are undefined. Figure 23.20 Switching between User MAT and User Boot MAT 889 Procedure for switching to the user boot MAT (3) Execute four NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (3) Execute four NOP instructions before accessing the user MAT. Address amended EB0 to EB15 H'000000 H'001000 H'002000 H'003000 H'004000 H'005000 H'006000 H'007000 H'008000 ... H'0FFFFF 24.8.1 Switching between User MAT and User Boot MAT Description amended (2) To ensure that the MAT that has been switched to is accessible, execute eight NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 12-Kbyte memory space. If access goes beyond the 12-Kbyte space, the values read are undefined. Figure 24.20 Switching between User MAT and User Boot MAT Figure amended Procedure for switching to the user boot MAT (3) Execute eight NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (3) Execute eight NOP instructions before accessing the user MAT. SH7058S/SH7059 Figure 24.19 Programming of Tuned Data
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Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 23.8.2 Interrupts during Programming/Erasing (2) Interrupts during programming/erasing 892, 893 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. 23.8.3 Other Notes 893, 894 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 40 MHz, the download for each program takes approximately 75 s at maximum. 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 23.11 lists the maximum and minimum intervals for initiating the user branch processing when the CPU clock frequency is 40 MHz. Table 23.11 Initiation Intervals of User Branch Processing
Processing Name Programming Erasing Maximum Interval Approximately 1 ms Approximately 5 ms Minimum Interval Approximately 17 s Approximately 17 s
SH7058S/SH7059 24.8.2 Interrupts during Programming/Erasing (2) Interrupts during programming/erasing Description amended 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If . flash memory that is being programmed or erased is accessed, the error protect state is entered, and programming or erasing is aborted. .
5. When a transition is made to sleep mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. 24.8.3 Other Notes Description amended 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 80 MHz, the download for each program takes approximately 305 s at maximum. 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 24.11 lists the minimum and maximum user branch processing intervals when the CPU clock frequency is 80 MHz. Table 24.11
Processing Name Programming Erasing
User Branch Processing Intervals
Maximum Interval Approximately 1 ms Approximately 5 ms Minimum Interval Approximately 19 s Approximately 19 s
Table and title amended
However, when operation is done with CPU clock of 40 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 23.12. Table 23.12 Initial User Branch Processing Time
However, when operation is done with CPU clock of 80 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 24.12. Table 24.12 Intervals Until Start of User Branch Processing . Table and title amended
Processing Name Programming Erasing Max. Approximately 500 s Approximately 2300 s Min. Approximately 500 s Approximately 1000 s
Processing Name Programming Erasing
Max. Approximately 113 s Approximately 85 s
Min. Approximately 113 s Approximately 45 s
Rev.3.00 Mar. 12, 2008 Page xlvii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 23.8.3 Other Notes 894 4. State in which AUD operation is disabled and interrupts are ignored Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 40 MHz after the reset signal is released) 24.8.3 Other Notes Description amended 4. State in which AUD operation is disabled and interrupts are ignored Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 80 MHz after the reset signal is released) 7. FWE pin state Newly added 23.9 Programmer Mode 894 In programmer mode, set the mode pins as shown in table 23.13, and provide a 6-MHz input-clock signal. 23.9.1 Pin Arrangement of Socket Adapter Figure 23.24 Mapping of On-Chip Flash Memory 895 On-chip ROM space (user MAT) On-chip ROM space (user MAT) 1 Mbyte Address in PROM mode H'0,0000 to H'F,FFFF On-chip ROM space (user boot MAT) On-chip ROM space (user boot MAT) 8 kbytes Address in MCU mode H'0000,0000 to H'0000,1FFF Address in PROM mode H'0,0000 to H'0,1FFF 24.9 Programmer Mode Description amended In programmer mode, set the mode pins as shown in table 24.13, and provide a 6-MHz input-clock signal. This enables this LSI to operate at 48 MHz. 24.9.1 Pin Arrangement of Socket Adapter Figure 24.24 Mapping of On-Chip Flash Memory Figure amended On-chip ROM space (user MAT) On-chip ROM space (user MAT) 1 Mbyte Address in PROM mode H'00,0000 to H'0F,FFFF On-chip ROM space (user boot MAT) On-chip ROM space (user boot MAT) 12 Kbytes Address in MCU mode H'0000,0000 to H'0000,2FFF Address in PROM mode H'0,0000 to H'0,2FFF SH7058S/SH7059
Rev.3.00 Mar. 12, 2008 Page xlviii of xc REJ09B0177-0300
Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) 23.9.1 Pin Arrangement of Socket Adapter Figure 23.25 Pin Arrangement of Socket Adapter 896
SH7058F Pin No. 7 8 9 10 12 14 15 16 17 18 19 21 23 24 25 26 27 28 29 31 63 64 65 66 67 68 69 71 218 230 226 56 11,20,39,42,43,46,49,52,55,57, 59,70,75,83,100,101,119,120, 128,139,148,172,187,194,203, 212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 58 53 51 60 61 62 30,161,225 Other Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 CE OE WE FWE Vcc
Socket Adapter (40-Pin Conversion)
SH7058S/SH7059 24.9.1 Pin Arrangement of Socket Adapter Figure 24.25 Pin Arrangement of Socket Adapter Figure amended BP-272 and Note * added
SH7058SF Pin No. BP-272 B3 D4 C4 A3 B4 A4 C5 B5 A5 D6 B6 A6 C7 B7 A7 D8 C8 B8 A8 D9 C9 D15 B18 A19 C18 B19 B20 C17 C19 P1 K2 L3 D14 D5,C6,A10,C11,A12,C12,C13, D13,B14,C15,A16,C16,D16,F17, F18,K19,K20,T20,T19,U19,U16, V15,V9,U6,V5,U4,P3,J3,H4 A9,B13,B15,D7,B12,D11,C14,F19, G3,G17,E20,J4,J20,U20,J9 to 12, K9 to 12,L9 to 12,M1,M9 to 12,P4, T18,U5,U9,V6,V16,W11 C10 B16 A15 A14 A17 B17 A18 B9,Y11,M2 FP-256H 7 8 9 10 12 14 15 16 17 18 19 21 23 24 25 26 27 28 29 31 33 63 64 65 66 67 68 69 71 218 230 226 56 11,20,37,39,42,43,46,49,52,55, 57,59,70,75,83,100,101,119, 120,128,139,148,172,187,194, 203,212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 34 58 53 51 60 61 62 30,161,225 Other Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 D0 D1 D2 D3 D4 D5 D6 D7 CE OE WE FWE Vcc Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 9 8 19 18 17 16 15 14 13 12 2 20 3 4 1,40 11,30 5,6,7 Vss A21 RES XTAL EXTAL PLLVcc PLLCAP PLLVss VCL NC (OPEN) Capacitor PLL circuit Power-on reset circuit Oscillator circuit Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18*1 A19*1 A20*1 I/00 I/01 I/02 I/03 I/04 I/05 I/06 I/07 CE OE WE FWE Vcc Vss NC
HN27C4096HG (40 pins) Pin Name Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 9 19 18 17 16 15 14 13 12 2 20 3 4 1,40 11,30 5,6,7 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 I/00 I/01 I/02 I/03 I/04 I/05 I/06 I/07 CE OE WE FWE Vcc Vss NC A20 A19
Legend: FWE : Flash-write enable I/07 to 0 : Data I/O A21 to 0 : Address input CE : Chip enable OE : Output enable WE : Write enable Note: *With using the HN27C4096HG as the base, unused I/O pins are adopted to make up for the shortage of address pins.
Vss RES XTAL EXTAL PLLVcc PLLCAP PLLVss VCL NC (OPEN) Capacitor PLL circuit
Power-on reset circuit Oscillator circuit
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